In general, a memory device receives a power voltage (VDD) and a ground voltage (VSS) from the outside, and generates and uses an internal voltage required for internal operation. A voltage required for internal operation of the semiconductor memory device includes an internal power (VCORE) supplied to a memory core region, a high voltage (Vpp) used upon driving of a word line or overdriving and a back bias voltage (VBB) supplied as a bulk voltage of an NMOS transistor in the core region.
Also, the internal voltage includes a cell plate voltage (VCP) used as a plate voltage of a memory cell capacitor and a bit line precharge voltage (VBLP) used to precharge a bit line. In general, the cell plate voltage (VCP) and the bit line precharge voltage (VBLP) are generated from the internal power (VCORE) and are generated to a half level of the internal power (VCORE) to minimize current consumption.
FIG. 1 is a circuit diagram illustrating a conventional internal voltage generation circuit.
As illustrated, the conventional internal voltage generation circuit is a circuit for generating a cell plate voltage VCP or a bit line precharge voltage VBLP, and voltage-divides the internal power VCORE through a plurality of resistance elements R10-R13 and drives the internal voltage VCP/VBLP by comparing a level of a voltage of a node nd10 generated to a half level of the internal power VCORE and a level of the internal voltage VCP/VBLP.
Operation of the internal voltage generation circuit illustrated in FIG. 1 will be described in more detail.
Levels of pull-up driving signal PDRV and pull-down driving signal NDRV are regularly maintained when the level of the internal voltage VCP/VBLP is the half level of the internal power VCORE, i.e., there is no variation, the internal voltage VCP/VBLP is driven by a regular current and is maintained at a regular level.
In this state, if the level of the internal voltage VCP/VBLP is lowered below the voltage of the node nd10, the levels of the pull-up driving signal PDRV and the pull-down driving signal NDRV are gradually decreased and a turn-on degree of a PMOS transistor P16 becomes larger than a turn-on degree of an NMOS transistor N18. Accordingly, the level of the internal voltage VCP/VBLP is increased. Also, if the level of the internal voltage VCP/VBLP is raised above the voltage of the node nd10, the levels of the pull-up driving signal PDRV and the pull-down driving signal NDRV are gradually increased and the turn-on degree of the NMOS transistor N18 becomes larger than the turn-on degree of the PMOS transistor P16. Accordingly, the level of the internal voltage VCP/VBLP is decreased. In other words, the internal voltage generation circuit controls so that the level of the internal voltage VCP/VBLP is generated to a half level of the internal power VCORE.
However, in the conventional internal voltage generation circuit of FIG. 1, a driving force for driving the internal voltage VCP/VBLP is considerably decreased at a low temperature as compared to a high temperature.
Referring to FIG. 2, currents for driving the internal voltage VCP/VBLP (hereinafter, referred to as ‘driving current’) at a high temperature (90° C.) and a low temperature (−40° C.) when the internal voltage VCP/VBLP is varied from 0.4 V to 0.8 V are compared. That is, at a high temperature (90° C.), the driving current is 1.1 mA if the internal voltage VCP/VBLP is lowered to 0.5 V and the driving current is 2.6 mA if the internal voltage VCP/VBLP is raised to 0.7 V. On the other hand, at a low temperature (−40° C.), the driving current is 0.24 mA if the internal voltage VCP/VBLP is lowered to 0.5 V and the driving current is −0.3 mA if the internal voltage VCP/VBLP is raised to 0.7 V. Here, the driving current is the current supplied through the PMOS transistor P16 and the NMOS transistor N18 to drive the internal voltage VCP/VBLP. The positive (+) driving current means that the internal voltage VCP/VBLP is pulled up as the current supplied through the PMOS transistor P16 is larger than the current discharged through the NMOS transistor N18, and the negative (−) driving current means that the internal voltage VCP/VBLP is pulled down as the current supplied through the PMOS transistor P16 is smaller than the current discharged through the NMOS transistor N18.
As such, since the driving current is considerably decreased at a low temperature (−40° C.) as compared to a high temperature (90° C.), it takes too much time to reset the internal voltage VCP/VBLP with a varied level to a half level of the internal voltage VCORE.